14 nanometer
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The 14 nm process refers to the
MOSFET The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a type of field-effect transistor (FET), most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate, the voltage of which d ...
technology node Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuit (IC) chips such as modern computer processors, microcontrollers, and memory chips such as NAND flash and DRAM that are pres ...
that is the successor to the
22nm The 22 nm node is the process step following 32 nm in CMOS MOSFET semiconductor device fabrication. The typical half-pitch (i.e., half the distance between identical features in an array) for a memory cell using the process is around 22  nm. ...
(or 20nm) node. The 14nm was so named by the
International Technology Roadmap for Semiconductors The International Technology Roadmap for Semiconductors (ITRS) is a set of documents produced by a group of semiconductor industry experts. These experts are representative of the sponsoring organisations which include the Semiconductor Industry A ...
(ITRS). Until about 2011, the node following 22nm was expected to be 16nm. All 14nm nodes use FinFET (fin field-effect transistor) technology, a type of
multi-gate MOSFET A multigate device, multi-gate MOSFET or multi-gate field-effect transistor (MuGFET) refers to a metal–oxide–semiconductor field-effect transistor (MOSFET) that has more than one gate on a single transistor. The multiple gates may be control ...
technology that is a non-planar evolution of planar silicon
CMOS Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss", ) is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFE ...
technology. Samsung Electronics taped out a 14 nm chip in 2014, before manufacturing 10 nm class NAND flash chips in 2013. The same year, SK Hynix began mass-production of 16nm NAND flash, and TSMC began 16nm FinFET production. The following year, Intel began shipping 14nm scale devices to consumers.


History


Background

The basis for sub-20nm fabrication is the FinFET (Fin field-effect transistor), an evolution of the
MOSFET The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a type of field-effect transistor (FET), most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate, the voltage of which d ...
transistor. FinFET technology was pioneered by Digh Hisamoto and his team of researchers at
Hitachi () is a Japanese multinational corporation, multinational Conglomerate (company), conglomerate corporation headquartered in Chiyoda, Tokyo, Japan. It is the parent company of the Hitachi Group (''Hitachi Gurūpu'') and had formed part of the Ni ...
Central Research Laboratory in 1989. 14 nm resolution is difficult to achieve in a polymeric resist, even with electron beam lithography. In addition, the chemical effects of
ionizing radiation Ionizing radiation (or ionising radiation), including nuclear radiation, consists of subatomic particles or electromagnetic waves that have sufficient energy to ionize atoms or molecules by detaching electrons from them. Some particles can travel ...
also limit reliable resolution to about 30 nm, which is also achievable using current state-of-the-art
immersion lithography Immersion lithography is a photolithography resolution enhancement technique for manufacturing integrated circuits (ICs) that replaces the usual air gap between the final lens and the wafer surface with a liquid medium that has a refractive inde ...
. Hardmask materials and
multiple patterning Multiple patterning (or multi-patterning) is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. It is expected to be necessary for the 10 nm and 7 nm node se ...
are required. A more significant limitation comes from plasma damage to low-k materials. The extent of damage is typically 20 nm thick, but can also go up to about 100 nm. The damage sensitivity is expected to get worse as the low-k materials become more porous. For comparison, the atomic radius of an unconstrained silicon is 0.11 nm. Thus about 90 Si atoms would span the channel length, leading to substantial leakage. Tela Innovations and Sequoia Design Systems developed a methodology allowing double exposure for the 16/14 nm node circa 2010. Samsung and Synopsys have also begun implementing double patterning in 22 nm and 16 nm design flows.
Mentor Graphics Siemens EDA is a US-based electronic design automation (EDA) multinational corporation for electrical engineering and electronics, headquartered in Wilsonville, Oregon. Founded in 1981 as Mentor Graphics, the company was acquired by Siemens in ...
reported taping out 16 nm test chips in 2010. On January 17, 2011, IBM announced that they were teaming up with ARM to develop 14 nm chip processing technology. On February 18, 2011, Intel announced that it would construct a new $5 billion semiconductor fabrication plant in Arizona, designed to manufacture chips using the 14 nm manufacturing processes and leading-edge 300 mm wafers. The new fabrication plant was to be named Fab 42, and construction was meant to start in the middle of 2011. Intel billed the new facility as "the most advanced, high-volume manufacturing facility in the world," and said it would come on line in 2013. Intel has since decided to postpone opening this facility and instead upgrade its existing facilities to support 14-nm chips. On May 17, 2011, Intel announced a roadmap for 2014 that included 14 nm transistors for their Xeon, Core, and Atom product lines.


Technology demos

In the late 1990s, Hisamoto's Japanese team from
Hitachi () is a Japanese multinational corporation, multinational Conglomerate (company), conglomerate corporation headquartered in Chiyoda, Tokyo, Japan. It is the parent company of the Hitachi Group (''Hitachi Gurūpu'') and had formed part of the Ni ...
Central Research Laboratory began collaborating with an international team of researchers on further developing FinFET technology, including TSMC's Chenming Hu and various UC Berkeley researchers. In 1998, the team successfully fabricated devices down to a 17nm process. They later developed a 15nm FinFET process in 2001. In 2002, an international team of researchers at UC Berkeley, including Shibly Ahmed (Bangladeshi), Scott Bell, Cyrus Tabery (Iranian), Jeffrey Bokor, David Kyser, Chenming Hu (
Taiwan Semiconductor Manufacturing Company Taiwan Semiconductor Manufacturing Company Limited (TSMC; also called Taiwan Semiconductor) is a Taiwanese multinational semiconductor contract manufacturing and design company. It is the world's most valuable semiconductor company, the world' ...
), and Tsu-Jae King Liu, demonstrated FinFET devices down to
10 nm The following are examples of orders of magnitude for different lengths. __TOC__ Overview Detailed list To help compare different orders of magnitude, the following list describes various lengths between 1.6 \times 10^ metres and 10^ ...
gate length. In 2005, Toshiba demonstrated a 15 nm FinFET process, with a 15 nm gate length and 10 nm fin width, using a sidewall spacer process. It has been suggested that for the 16 nm node, a logic transistor would have a gate length of about 5 nm. In December 2007, Toshiba demonstrated a prototype memory unit that used 15-nanometre thin lines. In December 2009, National Nano Device Laboratories, owned by the Taiwanese government, produced a 16 nm SRAM chip. In September 2011, Hynix announced the development of 15 nm NAND cells. In December 2012, Samsung Electronics taped out a 14 nm chip. In September 2013, Intel demonstrated an Ultrabook laptop that used a 14 nm Broadwell CPU, and Intel CEO
Brian Krzanich Brian Matthew Krzanich (born May 9, 1960) is an American engineer and Krzanich joined Intel as an engineer in 1982 and served as chief operating officer (COO) before being promoted to CEO in May 2013. As CEO, Krzanich was credited for diversifyin ...
said, " PUwill be shipping by the end of this year." However, shipment was delayed further until Q4 2014. In August 2014, Intel announced details of the 14 nm microarchitecture for its upcoming Core M processors, the first product to be manufactured on Intel's 14 nm manufacturing process. The first systems based on the Core M processor were to become available in Q4 2014 — according to the press release. "Intel's 14 nanometer technology uses second-generation tri-gate transistors to deliver industry-leading performance, power, density and cost per transistor," said Mark Bohr, Intel senior fellow, Technology and Manufacturing Group, and director, Process Architecture and Integration. In 2018 a shortage of 14 nm fab capacity was announced by Intel.


Shipping devices

In 2013, SK Hynix began mass-production of 16nm NAND flash, TSMC began 16nm FinFET production, and Samsung began 10nm class NAND flash production. On September 5, 2014, Intel launched the first three Broadwell-based processors that belonged to the low-TDP Core M family: Core M-5Y10, Core M-5Y10a, and Core M-5Y70. In February 2015, Samsung announced that their flagship smartphones, the Galaxy S6 and S6 Edge, would feature 14 nm Exynos systems on chip (SoCs). On March 9, 2015, Apple Inc. released the "Early 2015" MacBook and MacBook Pro, which utilized 14 nm Intel processors. Of note is the i7-5557U, which has Intel Iris Graphics 6100 and two cores running at 3.1 GHz, using only 28 watts. On September 25, 2015, Apple Inc. released the iPhone 6S & 6S Plus, which are equipped with "desktop-class" A9 chips that are fabricated in both 14 nm by Samsung and 16 nm by TSMC (Taiwan Semiconductor Manufacturing Company). In May 2016, Nvidia released its GeForce 10 series GPUs based on the
Pascal Pascal, Pascal's or PASCAL may refer to: People and fictional characters * Pascal (given name), including a list of people with the name * Pascal (surname), including a list of people and fictional characters with the name ** Blaise Pascal, Fren ...
architecture, which incorporates TSMC's 16 nm FinFET technology and Samsung's 14 nm FinFET technology. In June 2016, AMD released its Radeon RX 400 GPUs based on the
Polaris Polaris is a star in the northern circumpolar constellation of Ursa Minor. It is designated α Ursae Minoris ( Latinized to ''Alpha Ursae Minoris'') and is commonly called the North Star or Pole Star. With an apparent magnitude that ...
architecture, which incorporates 14 nm FinFET technology from Samsung. The technology was licensed to GlobalFoundries for dual sourcing. On August 2, 2016, Microsoft released the
Xbox One S The Xbox One is a home video game console developed by Microsoft. Announced in May 2013, it is the successor to Xbox 360 and the third base console in the Xbox series of video game consoles. It was first released in North America, parts of ...
, which utilized 16 nm by TSMC. On March 2, 2017, AMD released its Ryzen CPUs based on the Zen architecture, incorporating 14 nm FinFET technology from Samsung which was licensed to GlobalFoundries for GlobalFoundries to build. The NEC SX-Aurora TSUBASA processor, introduced in October 2017, uses a 16nm FinFET process from TSMC and is designed for use with NEC SX supercomputers. On July 22, 2018, GlobalFoundries announced their 12 nm Leading-Performance (12LP) process, based on a licensed 14LP process from Samsung. In September 2018 Nvidia released GPUs based on their Turing (microarchitecture), which were made on TSMC's 12 nm process and have a transistor density of 24.67 million transistors per square millimeter.


14 nm process nodes

Lower numbers are better, except for transistor density, in which case is the opposite. Transistor gate pitch is also referred to as CPP (contacted poly pitch), and interconnect pitch is also referred to as MMP (minimum metal pitch).


References

{{DEFAULTSORT:14 nanometre *00014 Bangladeshi inventions Iranian inventions South Korean inventions Taiwanese inventions